Project



COURSE MAJOR PROJECT INFORMATION

Up to four students can join together on a report. The contents of the report written and implemented by each student must be clearly defined. Students must create independent work for each of the major sections below. You can share the Abstract, Introduction and Background, and Conclusions section. All other sections should be repeated for each student.

General Description:

The Major Project (MP) for ELEC 5804 is an important component of the course. The major project is application oriented, and meant to expand your knowledge of integrated circuit design tools. You will apply the basic knowledge gained from doing the assignments, but you will have to learn techniques not covered in the assignments in order to complete the project.

Project Topics:
Here is a list of possible projects. You don't have to do one of these projects, instead you can suggest your own project. Proposals (a one page description) for alternative projects will be reviewed and accepted on a case by case basis. If you prefer a project that does not fit well with the marking scheme 

  • Synthesizable microprocessor
  • LMS adaptive filter
  • RLS adaptive filter
  • Digital filter
  • Echo canceller
  • SPI (Serial Programmable Interface)
  • GMSK modulator
  • Graphics accelerator (e.g. hardware line generation)
  • Image processor (e.g. blit, edge detection)
You are free to choose any available VERILOG or VHDL code that you find on-line and use that for your project.

Report Format and Contents:

I expect everyone can present their work clearly and concisely. Here are some guidelines:

Cover Page: The cover page should contain the title of the report, and a sub-heading indicating that it is a final project report submitted in lieu of an exam. Include the date, your name (names if more than one person), and student ID number(s).

Introduction : Introduce the reader to the work. Use non-technical language. Do not give numerical results. Describe the rest of the report.

Background and Theory: Discuss the need for your design. Present the background theory in some depth. For example, if you are doing a digital filter, provide at least a page or two on how digital filters operate.

Algorithm Design: Indicate what design techniques you used to arrive at your design. If you used particular tools, then discuss how these tools were used.

Implementation: Discuss your implementation. Describe key schematics and code. Discuss your test strategy.

Simulations: Discuss simulated results and the test benches used.

Synthesis: Discuss synthesis-related issues. Provide schematics for synthesized designs.

Layout and Verification: Describe the layout and give screen captures of the layout.

Results and Discussion: Quantify your design (speed, area, power. Etc.). Discuss problems in the design and implementation process. Suggest areas of research or improvement.

APPENDICES: Include things like: Code, Simulations, Block Diagrams

Report Marking Scheme:

Abstract
The abstract should be roughly one half page in length. Summarize your most important contributions, and give any numerical simulation results you care to report.
5 marks


Introduction and Background
Introduce your project in a way that will interest a casual technical reader. Frame your topic in terms of an example application. You should give some background material pertaining to your project. There is no need to go into an in-depth discussion. As an example, if you do the image processing chip, then you can give some background into image processing hardware including desired graphics operations, desired operating speed, and current generation hardware. You should aim for approximately four pages for this section of your report.
5 marks


Theory
The contents of the theory section of the report is highly dependent upon the topic of the major project that you choose. For example, if you decide to do a digital filter implementation, then you should have some basic theory concerning digital filters, the spectral response of digital filters, the effects of finite word length on the accuracy of the filter, etc. You should not extensively repeat textbook material in this section of your report. Discuss the major aspects of the theory relating to your project, and include references to textbooks, journal publications, conference proceedings, and theses as appropriate. Although the length of the theory section of your report will be dependent upon the complexity of your chosen project, you should aim for between five and ten pages for this section of the report.
10 marks


Design technique and results
You should describe the design techniques you followed in order to arrive at your final design. Include a description of the various iterations required to reach the final design. If you followed a particular design flow or methodology, you should describe this in detail. If appropriate, include a flowchart of your design methodology. You should describe any assumptions used during the design of your project. Describe trade-offs required to complete the design. Comment on the complexity of the design. Comment on the performance of the design with respect to a target application of your choosing. This section of your report should be approximately eight pages long.
10 marks


Implementation
Describes the implementation of your design. This section should include an overview of your code (if you utilize Verilog or VHDL) , including program flowcharts or state machines as appropriate. You should present your work in terms of pseudocode, and relate your pseudocode to your complete code which must appear in an appendix. If portions of your code are not synthesizable, comment on this and explain why. If you have written code so that it is synthesized in a particular way, described why this approach was taken, and described the technique that you followed. This section of the report should be about ten pages long.
15 marks


Simulations (test coverage, relevance, presentation)
You must perform simulations to verify the functionality of your design. As part of your simulation effort, you'll need to construct a test bench that will apply test signals to your design. Document your test bench, and fully describe your test methodology. Indicate which performance characteristics you are attempting to extract from simulations, and describe your technique. If you are simulating a digital design, describe your test coverage. Give several examples of your simulation results. Provide a summary of all the simulation results.
15 marks


Synthesis discussion and resulting schematics
You will need to synthesize your final Verilog code. In this section of the report, give a fairly in-depth discussion of the results obtained during the synthesis phase. You should examine your Verilog code and the resulting schematics, and find correspondences between them. For example, if a certain section of your Verilog code produces a large schematic, you should discover and explain why. If the synthesizer appears to create schematics that are unreasonably complicated or unnecessarily complex, comment on how a human might do a better job. If you see patterns in the synthesized schematic, try to discover and explain the origin of these patterned structures. Provides summary information about your synthesized schematic, including the number and types of gates and the expected layout area.
10 marks


Layout and Verification
The layout and verification phase of your project is optional. For those students who choose to do layout and verification of the design, ten bonus points are possible. The maximum mark on your major project is still 100%, but you will be marked out of 110 points. You'll need to generate the design layouts, do the power routing, route all signals to the pad frame, and implement a pad frame. You'll need to do a design rule check of the total layout, and also perform a layout versus schematic check. Include in your report your DRC results and your LVS results. Also include plots of your chip layout, and any other material you think is appropriate.
+10 marks


Results and Discussion
The results and discussion section of your project is where you get to comment on the overall design strategy that you followed, and the results that you obtained. If appropriate, you should compare your results to a published implementation of a similar circuit. If other students in the class design similar circuits to yours, then you can compare your results to your colleagues' results.
10 marks


Verilog code with comments, and synthesized schematics
Include all of your Verilog code. You should also include all of your synthesized schematics. Marks will be deducted for code that is not properly commented. You should comment on your code in such a way that if you were to look at your code five years from now, you would have no problem understanding what you had written. For your schematics, indicate the correspondence between the schematic and the code.
10 marks


Bibliography
Your bibliography should be in standard IEEE numerical format. Use the reference format as shown in the IEEE Journal of Solid State Circuits. You should search the IEEE web site to find the most recent template for this reference style. Include references for journal publications, graduate student records, theses, conference proceedings, and textbooks. Depending upon the complexity of your project, you should have between eight and 20 references. Some students will have more references if they are voracious readers.
5 marks


Overall presentation and effort
Exceptional reports will get five marks for overall presentation and effort. Well done reports that do not fall in the exceptional category will receive between one mark and four marks. Reports that are poorly presented or that demonstrate a lack of effort will receive zero of the five possible marks.
5 marks


Total: 100 marks

Note: the approximate page counts given above are only meant as a guide. You are free to use as many pages as you like to fully describe your work.


ALSO NOTE: Not every report will have Verilog or VHDL code. Some reports will be more focused on analog design. Not every report will contain synthesized logic.