L2

NOTE: When watching all the videos below, ensure that you play them full screen so that everything is readable (you can do this by clicking on the YouTube icon in the lower righthand corner to watch in YouTube, which allows you to view the videos at the full resolution of 1280x720). Also, if you try to watch them on a mobile device through 3G, YouTube downgrades the resolution and they look horrible. Probably you'll want to bring headphones to the lab in order to hear the audio.

NOTE: The name of the server has changed since I made these videos. So whenever I type or say "macopeland" replace that with "boothroyd". This is very important!

Part 1: Preparing for Assignment 2.
Follow the steps in the video below to prepare for Assignment 2:

Part 2: Creating a Library
We could use the library from assignment 1, but just to make sure that everyone is starting from the same point, let's create a new library for assignment 2 as follows:
2.1) Go to the Library Manager Window. 
2.2) Select: File --> New --> Library
2.3) For the "Name", enter "assignment02"
2.4) For "Technology File", select "Attach to an existing techfile".
2.5) Click OK, and in the form that appears, on "Attach to Technology Library", select "gpdk090", and click OK. The library "assignment02" is then created. You should see it added to the list of libraries available in the Library Manager window.
The video below demonstrates steps 2.1-2.5:
Part 3: Examination of a Layout
First you need to make a layout cellview.
3.1) In the Library Manager window, click on "assignment02" and then go to File-->New-->Cellview. A window will pop up. Fill in the information so that you create a new cell of name “invLayout” and view “layout”.
3.2) Click OK and then the "Virtuoso" layout editing window will open. This is where you create your layout.  
3.3) Next we will add an existing standard cell from the PDK library. Do this by pressing the "i" key (insert instance) or selecting Create-->Instance from the Virtuoso window menu. A window pops up called "Create Instance".
3.4) There is a Browse button within this window. Click the Browse button, and the Library Browser window pops up. In the library browser window, ensure that Categories is selected, click on gsclib090, then click on INV in the categories section, and then click on INVX1 under Cell, and then layout under View. 
3.5) Click the Close button, and you should see the Create Instance window is now filled in with the required information.
3.6) Click the Hide button and move the cursor around inside the Virtuoso window. You should see a standard cell outline following your cursor motions. Just left-click somewhere within the Virtuoso layout area in order to place an instance of the layout cellview. Then hit your Esc key to exit the insert instance mode.
3.7) Type the "f" key to get a full view of the layout. Depending on your Cadence settings you will see either the outline of the standard cell or the entire standard cell. Get the full layout view showing the layers used in the layout by pressing Shift-f. You can use Ctrl-f to go back to an outline view.
3.8) The colors used for contacts in the layout make the contacts difficult to see. To fix this, go to the layers section of the virtuoso window, click on the little red triangle to get a drop-down menu, and select Edit Display Resources. Click on "contact" in the list at the left, and for the outline color, choose the bright green square. Click on Apply, and then File-->Exit. When the Saving Display Information window pops up, just say No.
3.9) The next step requires some experimentation on your part. You are required to use the layout editor to separate the layers used to construct the inverter and arrange them so they are clearly visible. As a hint to get started, read about layout hierarchy in the on-line manuals, and find the "flatten" command in the menus. Make sure you use the LSW settings to your advantage. You can selectively enable and disable different combinations of layers. Use Create-->Label to create labels for each of the layers.

3.10) Save your "exploded inverter" layout and close the cellview.
Parts 3.1 - 3.10 are demonstrated in the following video:
3.11) Create a new layout cellview and call it invToExt. Insert two instances of INVX1.  Flatten both of the inverters fully (Edit-->Hierarchy-->Flatten).
3.12) To demonstrate the Design Rule Checker in Cadence, we are going to modify one of the inverters and introduce a design rule violation. Zoom in on the inverter on the left side of your layout and add a small square of metal as shown  in the video. You may have to turn of "gravity" in order to get the new piece of metal as close as possible to the existing metal without touching. You can toggle gravity with the "g" key.
3.13) Now, run a DRC (design rule check). Go to Verify-->DRC. A window pops up. Set up the window as shown in the video below, and click ok.
3.14) The computer will churn away for a  few seconds, and some text will scroll in the main Cadence window. What Cadence is doing is checking your layout for design rule violations. When Cadence is finished, you should get a summary.
3.15) If you look in the layout window, you will notice that some markers have been inserted in your layout (you may have to refresh the window to see these appear). These markers are supposed to help you find the errors in the layout. For example, there should be a trapezoidal marker between the metal you added to the layout, and the metal that was already in the original inverter layout.
3.16) To find out what a particular marker means, go to Verify-->Markers-->explain, and then click on the marker. 
3.17) You should see that the piece of metal you added was placed too closely to the existing metal. We would have to move the metal further away to fix the problem.
3.18) Delete the the piece of metal that you added. Re-run the DRC. You should still see one error concerning “ptap”. Your job is to figure out the source of this error and fix the problem.
Parts 3.11 - 3.18 are demonstrated in the following video:

You may find that the DRC markers cause your remote sessions to get super slow. If so, the following video may help:



3.19) Once you've fixed all the design rule violations in your layout, do an Extract operation by going to Verify-->Extract. Fill in the form as shown in the video below, and then click on OK.
3.20) Look in your Library Manager window. You should see a new view listed for your invToExt cell, as shown below. This view is the extracted view from your layout.
3.21) Open the extracted view. Type Shift-f and you should see symbols are drawn on the extracted view to represent the extracted MOSFETs. The width and length of each MOSFET are given. 
3.22) Click on the gate for each MOSFET, and press the "q" (query) key. More information about each device is shown when you do so. 
Parts 3.19 - 3.22 are demonstrated in the following video:


Part 4: Custom Layout
In this section you will enter the schematic for an inverter and also enter the layout for the inverter. Then you will get Cadence to verify that your schematic matches your layout.
4.1) In the library manager click on the assignment02 library, then click File->New->Cell View. In the form the pops up, enter myInv as the Cell name, schematic as the View name, and click OK. Enter the schematic of the CMOS inverter as shown in the video below. Make sure that the type of pin used for the input is "Input", for the output is "Output", and for vdd and vss, use "InputOutput". Check and Save your inverter schematic and resolve any errors/warnings. 
4.2) In the library manager click on the assignment02 library, then click File->New->Cell View. In the form that pops up, enter myInv as the Cell name, layout as the View name, and click OK. Using the inverter layout that you previously examined as a reference, lay out the custom inverter as defined by the schematic above. The Design Rule Checker (DRC) can be invoked from the layout editor to find all design rule violations in your layout. They will be flagged as errors and must be resolved. On your layout, make sure that you provide supply and I/O pins using the create pin menu command. Use a "shape pin" to define the terminals in your layout such that they correspond to the terminals in the schematic. You have to make sure that the names of the pins are the same in the schematic and in the layout.
Once you have finished the layout and have resolved any DRC errors, perform a circuit extraction from your layout so that it can be verified against your schematic: Verify->Extract. Enter parasitics as the switch. Look for any errors and extract again after correcting them.
4.3) Running LVS (Layout vs. Schematic)
Open the extracted view of myInv. Select Verify->LVS. Under Create Netlist make sure schematic and extracted are checked. Fill in the pop-up form as shown in the video below.
Click Run. LVS will compare the layout and schematic views of the inverter and will show errors if there are differences. Click Output at the bottom of the LVS window and look for any matching errors. You are finished when there are no matching errors and the tools says the netlists match.
Parts 4.1 - 4.3 are demonstrated in the following two videos:



Part 5: Complex Layout Using Standard Cells
5.1) Make a new schematic and call it myBigDesign. Enter the schematic as shown in the video below.
5.2) Now create a layout view for the myBigDesign cell. Using cells from the PDK library, create the layout for the schematic. Try generating the layout as shown in the video. Also try generating the layout such that the cells are arranged as we discussed in class (i.e. in a row, such that power and ground abut).
5.3) Perform DRC, extraction, and LVS on your layout until it matches your schematic.
Parts 5.1 - 5.3 are demonstrated in the following video:


Part 6: Assignment Requirements
Your assignment hand-in must be typed and submitted as a PDF using the DropBox link that was emailed to the class. Other file formats will not be accepted. 

Important: Please name your file using this template:

STUDENT# - lastname - firstname - A1.pdf

Example: 100271828-MacEachern-Leonard-A1.pdf

 You can choose the structure of your write up, but make sure that the following is included:
1) Submit the layout for the "exploded inverter" as discussed in Section 3.9. Make sure that you label all the layers. [5 points]
2) Explain all the DRC errors encountered in Sections 3.13-3.17.  [5 points]
3) Explain the DRC ptap error found in Section 3.18, and explain what you did to fix the error. [10 points]
4) From Part 4, submit your custom schematic and custom layout. Use pmos and nmos sizes that give you a switching point of VDD/2. In other words, choose the correct ratio of the mosfet sizes so that when the inverter switches its state, the switch occurs centred at an input voltage of VDD/2. Also submit the LVS report generated by Cadence. Discuss any DRC errors you made (not all of them, just give a few examples). Also discuss any LVS errors and how you fixed them. [10 points]
5) From Part 5, submit your custom schematic and custom layout. Also submit the LVS report generated by Cadence. Discuss any DRC errors you made (not all of them, just give a few examples). Also discuss any LVS errors and how you fixed them. [10 points]

6) From Part 5, explain the procedure you used to get a single row of standard cells in your layout. [10 points].
7) Extra effort (show me you can do something interesting with Cadence independently. ): [10 points]  This could be anything the demonstrates some self-learning with the tools. Some examples: try extracting and simulating your layout, try generating a few layouts with different optimization settings, etc.