L5


NOTE: THIS LAB IS NOT OFFERED IN 2019 FOR CREDIT. THESE MATERIALS HAVE BEEN LEFT ON-LINE FOR YOUR OWN SELF-LEARNING.


ELEC 5804 Assignment #5: Layout Synthesis with Encounter
Part 1: Introduction
This assignment continues where assignment #4 left off. In assignment #4 you had to synthesize a filter using a Verilog open core module. In this assignment we will continue the exercise and produce a prototype layout for this Verilog module.
SETUP FOR ASSIGNMENT #5
The following video demonstrates how to prepare for the assignment (directory set up). Just watch and then repeat the steps in your own directory.


In the video below I show you what you would need to do in order to produce files that can be used with Cadence Encounter. Basically, after the synthesis of the Verilog code is complete you simply save out the synthesized design to a file. You also write out your timing constraints to another file. These files are used in the Cadence Encounter tool as part of the overall routing strategy. Watch the video and you will see how it’s done. There’s no need for you to repeat this because I include the necessary files for you in the archive file as explained below.




Part 2: First Encounter
Ok, now that you've made it this far, it is time to start with Encounter. Encounter is a tool for doing placement of standard cells, chip floor planning, and routing. 
You are going to do an abbreviated run-through of the tool. The following steps will be covered:
  • starting First Encounter
  • importing a design
  • floorplanning the chip
  • creating power rings
  • creating power stripes
  • placing the standard cells
  • routing the standard cells
  • examination of the layout

Note that clock tree generation, power stripe connections, pad placement, etc. are not covered and would be required for an actual chip layout.
Watch the two videos below, and then use what you learned to answer the questions that were emailed to you as a Google Form.